The trend in semiconductor fabrication technology continues towards increasing circuit density, and thus further microminiaturization of semiconductor structures is highly desirable. A semiconductor structure in this context is defined as any region, device, component, or element thereof that can be grown, formed, diffused, implanted, deposited, etc. into or onto a semiconductor substrate. For example, the gate conductor in today's high speed semiconductor transistor devices has diminished to a horizontal width of 0.4.times.10.sup.-6 meters, and it is foreseen that the horizontal width will further decrease to 0.1.times.10.sup.-6 meters.
A stud is an electrically conductive element which contacts a semiconductor structure and allows for electrical connection with another semiconductor structure. Typically, a stud is fabricated so as to contact the top of the structure. Accordingly, as the horizontal width of a semiconductor structure decreases, the available area for forming a stud to contact the top of the structure also decreases. Thus, a high degree of accuracy is required to properly form and align a stud so as to contact a microminiaturized semiconductor structure. In other words, increased microminiaturization of semiconductor structures leads to the problem of decreased alignment error tolerance when fabricating a contact stud for contacting the top of such a structure.
Traditionally, in order to form a contact window for fabricating a stud for a semiconductor structure, a border is included around the edges of the contact window. Such a border generally has dimensions which are greater than the dimensions of the required contact window, and is used to insure that, even under worst case conditions, the contact window and stud will fall on top of the semiconductor structure. Further, the borders guard against the contact window and stud falling partially on the semiconductor structure and partially on an undesired region, such as the field oxide. In such a situation, the field oxide may be consumed by an overetch and a leakage path may be formed from the semiconductor structure to the substrate. However, an undesirable effect associated with using a border around a contact window is that the area required for forming a contact window and stud is significantly increased. Consequently, the maximum number of integrated circuits that can be packed into a given area on a chip becomes limited.
One attempt to form a contact window and stud for contacting the top of a semiconductor structure while maintaining circuit density makes use of a borderless fabrication method. In contrast to a bordered method, the borderless method does not require borders around the edges of the contact window. Accordingly, the amount of space required to form the contact window and stud is minimized so that, in comparison to the bordered method, a greater number of circuits can be packed into a given area on a chip. However, decreased alignment error tolerance associated with current day microminiaturization of semiconductor structures has made it exceedingly difficult to use a borderless method to form a contact window which falls directly on top of a structure without effectuating an undesired overetch, and resulting in a leakage path.
Moreover, borderless methods of fabricating studs generally result in only partially contacting the top of the semiconductor structure. Since the horizontal width of semiconductor structures has diminished to such a great extent, partial contact with such a structure frequently leads to problems of reliability. In other words, since the stud contacts only a portion of the top of the semiconductor structure, such contact may not provide adequate electrical connection to the structure for proper operation.